Technical Field
The present invention relates to transistor fabrication and, more particularly, to fabrication of unmerged source/drain fin field effect transistors.
Description of the Related Art
Fin field effect transistors (FinFETs) are commonly employed in modern semiconductor devices due to their small size and ease of fabrication. During fabrication of such devices, the fins may have additional material added to them through epitaxial growth. Increasing the fin size in this manner can improve various electrical properties of the device, in particular by decreasing the device resistance. Epitaxial growth can be conducted to an arbitrary degree, and the decreased device resistance scales continuously with fin size.
However, conventional epitaxial growth processes face certain challenges. In one technique, the epitaxial growth continues until a line of parallel fins merge with one another. However, fins at the ends of the line will have a significant amount of lateral growth, which increases the effective size of the device and can cause electrical failures due to, e.g., source/drain shorts or N/P shorts. In this case, epitaxial growth causes the device to become so large that it interferes with other devices on the chip, resulting in malfunctions and a lower device yield.
In another technique, the fins are grown through an epitaxial process, but are left unmerged. Due to fin pitch walking and other process variations, however, some it is likely that some of the fins will merge and others will not, resulting in variations in the electrical properties of the devices from one device to the next. This can be addressed by limiting the amount of epitaxial growth to such a degree that no expected variations would cause fins to merge, but this leads to a much higher device resistance than is desirable.